module control(input  [3:0] op, 
               output [2:0] alusrc,
               output     Acontrol,  MDRwrite,  Awrite, memwrite);  
   
   reg [6:0] 		    controls;               

  assign {alusrc, Acontrol,MDRwrite, Awrite, memwrite} = controls;

   always @(*)
     case(op)       
       4'b0100: controls <= 7'bxxx1110; //LOAD
       4'b0101: controls <= 7'bxxx1111; //STORE
       4'b0110: controls <= 7'bxxx1110; //LOADI
       4'b0111: controls <= 7'bxxx0111; //STOREI
       4'b1000: controls <= 7'b0000110; //AND
       4'b1001: controls <= 7'b0010110; //OR
       4'b1010: controls <= 7'b0100110; //ADD
       4'b1011: controls <= 7'b0110110; //SUB
       4'b1100: controls <= 7'b1000110; //INC
       4'b1101: controls <= 7'b0110110; //SUBI
       //default: controls <= 7'bxxxxxxx; //???   
     endcase // case(op) 
endmodule // control
